1. Technical Field
The present invention relates generally to memory controllers, and more particularly, to a random access memory controller having an adaptive row management policy.
2. Description of the Related Art
Memory subsystems, such as those implemented in present-day computing systems, typically employ memory controllers that interface random-access memory (RAM—typically dynamic RAM or DRAM) to a processing unit and provide various other support functions such as refresh control, buffering (caching) and timing support. Present high-speed RAM implementations such as Synchronous DRAM (SDRAM), double data rate (DDR) SDRAM are in common use and quad data rate (DDRII) SDRAM is expected to be in common use within the near future.
A memory core is typically organized as a storage cell array having rows and columns. A row is accessed by providing a first selector (which is usually an “active” row select command in present SDRAM and DDR devices) and a row address that select data from all of the cells in the row onto internal column bitlines after pre-charging the column bitlines to a known state. A read or write command and column address then select the bitline that corresponds to the exact memory cell requested for a data read. Alternative RAM designs select all of the cells in a column to row bitlines and then select the individual row bitline to provide the data output, which is generally an equivalent circuit.
Memory controllers typically provide the row management policy for the memory subsystem. Typically the row management policy for present SDRAM designs is to hold the last accessed row open after the end of an access or to always close the current row after each access. SDRAM implementations that provide for burst count presetting improve performance for burst cycles, but not between individual accesses to the SDRAM (which may be bursts or single accesses). In order to terminate the row holding behavior of the SDRAM, a special command called a “precharge” command is issued to the SDRAM by a special combination of the command signal lines, which is typically only issued upon a row address change. Older memory configurations hold and terminate rows under control of a row address select (RAS) signal which may be held active during subsequent accesses to multiple columns within the same row.
Adaptive memory controllers, such as that described in U.S. Pat. No. 6,556,952, have been implemented that study bank miss and bank hit performance and provide for reconfiguration of bank size. However, such implementations require memory arrays that accommodate a programmable number of memory banks, which are typically limited between two page sizes. The above-referenced patent provides techniques for reconfiguring page size, refresh rates and write buffer parameters, but not the mode of the DRAM access and the DRAM performance measuring techniques discussed therein are not adapted for controlling row management policy as page misses are weighted more lightly than page hits.
It is therefore desirable to provide a method and apparatus for providing an adaptive row management policy within a memory controller, whereby average latency of the memory subsystem is reduced. It is further desirable to provide a method and apparatus for selecting a row management policy in a memory controller at system run-time in conformity with a measurement of row access behavior in the system.